FIG. 9 shows a configuration of a conventional output signal generating device. This output signal generating device is applied, for example, to an apparatus that generates a signal for a motor inverter. The conventional output signal generating device is described with reference to FIG. 9 hereinafter. The output signal generating device includes a control circuit 100, a reference signal generating unit 102 and an output signal generating unit 104. The control circuit 100 and the reference signal generating unit 102 are connected to the output signal generating unit 104, respectively. The control circuit 100 outputs a control signal a such as a software command signal. The reference signal generating unit 102 outputs a reference signal b. The output signal generating unit 104 is composed of, for example, a comparator or the like and generates a signal corresponding to a comparison result between the control signal a and the reference signal b to output the generated signal as an output signal c.
FIG. 10 shows signal waveforms of respective units in FIG. 9 and timings. The following calculations are made in order to ascertain a state of the output signal c with implemented software in the control circuit 100.
Time for which the output signal c stays a high stateThi=T1+T−T2Time for which the output signal c stays a low stateTlow=T2−T1
The number of the output signals c increases, so that the above mentioned calculation process amount may increase. Therefore, as frequency of the output signal increases, the calculation process cycle of the software must be shorter.
In addition, a related art of an output signal generating device is also disclosed in Japanese Patent Application Laid-Open No. H8-19263 (Patent Document 1), for example. In this Patent Document 1, disclosed is a current detecting device with a PWM inverter type current detection. This current detecting device detects a DC-side current with one current sensor to detect an output current of each phase and calculates the difference of the DC-side current between pre- and post-switching per each phase. This makes it possible to detect the output current with the one current sensor although a plurality of current sensors have been required heretofore.
Also in Japanese Patent Application Laid-Open No. 2002-84760 (Patent Document 2), disclosed is an invention of a phase current calculation unit for calculating a phase current together with the configuration of the invention in the Patent Document 1. This phase current calculation unit calculates a phase current with a DC bus current value and a 3-phase voltage state on the timing of the current detection based on the fact that an inner product of a phase current vector and a phase voltage vector is identical to a DC busbar current. Since the invention in the Patent Document 2 makes it possible to obtain all phase currents at the time when two kinds of non-zero voltage vectors that certainly present during one PWM cycle are output, detection frequency of the DC bus current can be reduced.
The invention disclosed in each of the Patent Documents 1 and 2 relates to an output current detecting device for a PWM inverter and mainly aims at 3-phase current calculations at low cost and with small detection frequency.
Patent Document 1: Japanese Patent Application Laid-Open No. H8-19263
Patent Document 2: Japanese Patent Application Laid-Open No. 2002-84760